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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS9LPRS480 датащи(PDF) 13 Page - Integrated Device Technology |
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ICS9LPRS480 датащи(HTML) 13 Page - Integrated Device Technology |
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13 / 25 page  13 Integrated Circuit Systems, Inc. ICS9LPRS480 1391D—02/02/09 AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Crossing Point Variation ∆V CROSS Single-ended Measurement 140 mV 1,2,5 Frequency - CPU fCPU Spread Specturm On 198.8 200 MHz 1,3 Frequency - HTT fHTT Spread Specturm On 99.4 100 MHz 1,3 Long Term Accuracy ppmSpread Specturm Off -300 +300 ppm1,11 Rising Edge Slew Rate SRISE Differential Measurement 0.5 10 V/ns 1,4 Falling Edge Slew Rate SFALL Differential Measurement 0.5 10 V/ns 1,4 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 CPU, DIF HTT Jitter - Cycle to Cycle CPUJC2C Differential Measurement 150 ps 1,6 Accumulated Jitter tJACC See Notes 1 ns 1,7 Peak to Peak Differential Voltage VD(PK-PK) Differential Measurement 400 2400 mV 1,8 Differential Voltage VD Differential Measurement 200 1200 mV 1,9 Duty Cycle DCYC Differential Measurement 45 55 % 1 Amplitude Variation ∆V D Change in VD DC cycle to cycle -75 75 mV 1,10 CPU[1:0] Skew CPUSKEW10 Differential Measurement 100 ps 1 Notes on Electrical Characteristics: 1Guaranteed by design and characterization, not 100% tested in production. 3Minimum Frequency is a result of 0.5% down spread spectrum 6 Max difference of t CYCLE between any two adjacent cycles. 7 Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval. 8 VD(PK-PK) is the overall magnitude of the differential signal. 11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 4Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when crossing through this region. 9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD. VD(max) is the largest amplitude allowed. 2Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not important 10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC and ATIG PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Rising Edge Slew Rate tSLR Differential Measurement 2.5 8 V/ns 1,2 Falling Edge Slew Rate tFLR Differential Measurement 2.5 8 V/ns 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1 Minimum Output Voltage VLOW Includes undershoot -300 mV 1 Differential Voltage Swing VSWING Differential Measurement 300 mV 1 Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4 Crossing Point Variation VXABSVAR Single-ended Measurement 140 mV 1,3,5 Duty Cycle DCYC Differential Measurement 45 55 % 1 SRC, ATIG, Jitter - Cycle to Cycle SRCJC2C Differential Measurement 125 ps 1 SRC[5:0] Skew SRCSKEW Differential Measurement 250 ps 1 SB_SRC[1:0] Skew SRCSKEW Differential Measurement 100 ps 1 ATIG[2:0] Skew SRCSKEW Differential Measurement 100 ps 1 Notes on Electrical Characteristics: 1Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK |
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