3

Integrated

Circuit

Systems, Inc.

ICS9LPRS480

1391D—02/02/09

MLF Pin Description (Continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

33

GNDSB_SRC

GND

Ground pin for the SB_SRC outputs

34

VDDSB_SRC_IO

PWR

Power supply for differential SB_SRC outputs, nominal 1.05V to 3.3V

35

VDDSB_SRC

PWR

Supply for SB SRC PLL core, 3.3V nominal

36

SB_SRC0C_LPRS

OUT

Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt

resistor to GND and no 33 ohm series resistor needed

37

SB_SRC0T_LPRS

OUT

True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor

to GND and no 33 ohm series resistor needed

38

CLKREQ4#*

IN

Clock Request pin for SRC4 outputs. If output is selected for control, then that output is controlled

as follows:

0 = enabled, 1 = Low-Low

39

CLKREQ3#*

IN

Clock Request pin for SRC3 outputs. If output is selected for control, then that output is controlled

as follows:

0 = enabled, 1 = Low-Low

40

VDDSATA

PWR

Power supply for SATA core logic, nominal 3.3V

41

SRC6C/SATAC_LPRS

OUT

Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to

GND and no 33 ohm series resistor needed)

42

SRC6T/SATAT_LPRS

OUT

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)

43

GNDSATA

GND

Ground pin for the SRC outputs

44

CLKREQ2#*

IN

Clock Request pin for SRC2 outputs. If output is selected for control, then that output is controlled

as follows:

0 = enabled, 1 = Low-Low

45

CLKREQ1#*

IN

Clock Request pin for SRC1 outputs. If output is selected for control, then that output is controlled

as follows:

0 = enabled, 1 = Low-Low

46

GNDCPU

GND

Ground pin for the CPU outputs

47

VDDCPU_IO

PWR

Power supply for differential CPU outputs, nominal 1.05V to 3.3V

48

VDDCPU

PWR

Supply for CPU core, 3.3V nominal

49

CPUKG0C_LPRS

OUT

Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with

integrated series resistor. (no 33 ohm series resistor needed)

50

CPUKG0T_LPRS

OUT

True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series

resistor.(no 33 ohm series resistor needed)

51

PD#

IN

Enter /Exit Power Down.

0 = Power Down, 1 = normal operation.

52

GNDHTT

PWR

Ground pin for the HTT outputs

53

HTT0C_LPRS/66M

OUT

Complementary signal of low-power differential push-pull hypertransport clock with integrated

series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 1.8V

single ended 66MHz hyper transport clock

54

HTT0T_LPRS/66M

OUT

True signal of low-power differential push-pull hypertransport clock with integrated series

resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) /1.8V single

ended 66MHz hyper transport clock

55

VDDHTT

PWR

Supply for HTT clocks, nominal 3.3V.

56

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

57

REF2/SEL_27

I/O

14.318 MHz reference clock, 3.3V/3.3V Latched input to select 27MHz SS and non SS on SRC7

0 = 100MHz differential spreading SRC clock, 1 = 27MHz non-spreading singled clock on pin 5

and 27MHz spread clock on pin 6.

58

REF1/SEL_SATA

I/O

14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA

output

0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock

59

REF0/SEL_HTT66

I/O

14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock

Frequency.

0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock

60

GNDREF

GND

Ground pin for the REF outputs.

61

X1

IN

Crystal input, nominally 14.318MHz

62

X2

OUT

Crystal output, nominally 14.318MHz

63

VDD48

PWR

Power pin for the 48MHz outputs and core. 3.3V

64

48MHz_0

OUT

48MHz clock output.