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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS9LPRS480 датащи(PDF) 12 Page - Integrated Device Technology |
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ICS9LPRS480 датащи(HTML) 12 Page - Integrated Device Technology |
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12 / 25 page  12 Integrated Circuit Systems, Inc. ICS9LPRS480 1391D—02/02/09 Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Supply VoltageVDDxxx -3.3 GND + 3.9V V 1 Storage Temperature Ts - -65 150 °C 1 Ambient Operating Temp Tambient - 070 °C 1 Case Temperature Tcase - 115 °C 1 Input ESD protection HBM ESD prot - 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDxxx - 3.135 3.3 3.465 V 1 Input High Voltage VIH VDD = 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL VDD = 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Voltage - SEL_27 VIH VDD = 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage - SEL_27 VIL VDD = 3.3 V +/-5% VSS - 0.3 0.4 V 1 Input High Voltage - SEL_SATA VIH VDD = 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage - SEL_SATA VIL VDD = 3.3 V +/-5% VSS - 0.3 0.4 V 1 Input High Voltage - SEL_HTT66 VIH VDD = 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage - SEL_HTT66 VIL VDD = 3.3 V +/-5% VSS - 0.3 0.4 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 IIL1 VIN = 0 V; Inputs with no pull- up resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Low Threshold Input- High Voltage VIH_FS VDD = 3.3 V +/-5% 0.7 VDD + 0.3 V 1 Low Threshold Input- Low Voltage VIL_FS VDD = 3.3 V +/-5% VSS - 0.3 0.35 V 1 Operating Current IDD3.3OP 3.3V VDD current, all outputs driven 225 mA 1 Powerdown Current IDD3.3PD all diff pairs low/low 2 mA 1 Input Frequency Fi VDD = 3.3 V +/-5% 14.31818 MHz 2 Pin Inductance Lpin 7nH 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization TSTAB From VDD Power-Up or de- assertion of PD to 1st clock 1.8 ms 1 Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_PD CPU output enable after PD de-assertion 300 us 1 Tfall_PD PD fall time of 5 ns 1 Trise_PD PD rise time of 5 ns 1 SMBus Voltage VDDSMB 2.7 5.5 V 1 Low-level Output Voltage VOLSMB @ IPULLUP 0.4 V 1 Current sinking at VOL = 0.4 V IPULLUPSMB 46 mA 1 SMBCLK/SMBDAT Clock/Data Rise Time TRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SMBCLK/SMBDAT Clock/Data Fall Time TFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1Guaranteed by design and characterization, not 100% tested in production. Input Low Current Input Capacitance 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. |
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