TMS320F2812 datasheet(7/170 Pages) TI

7 / 170 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S – APRIL 2001 – REVISED MARCH 2011

List of Tables

2-1

Hardware Features

............................................................................................................... 14

2-2

Signal Descriptions

............................................................................................................... 18

3-1

Addresses of Flash Sectors in F2812 and F2811

........................................................................... 31

3-2

Addresses of Flash Sectors in F2810

......................................................................................... 31

3-3

Wait States

........................................................................................................................ 32

3-4

Boot Mode Selection

............................................................................................................. 35

3-5

Impact of Using the Code Security Module

................................................................................... 36

3-6

Peripheral Frame 0 Registers

.................................................................................................. 39

3-7

Peripheral Frame 1 Registers

.................................................................................................. 39

3-8

Peripheral Frame 2 Registers

.................................................................................................. 40

3-9

Device Emulation Registers

..................................................................................................... 41

3-10

XINTF Configuration and Control Register Mappings

....................................................................... 43

3-11

XREVISION Register Bit Definitions

........................................................................................... 43

3-12

PIE Peripheral Interrupts

........................................................................................................ 45

3-13

PIE Configuration and Control Registers

...................................................................................... 46

3-14

External Interrupts Registers

................................................................................................... 47

3-15

PLL, Clocking, Watchdog, and Low-Power Mode Registers

............................................................... 49

3-16

PLLCR Register Bit Definitions

................................................................................................. 51

3-17

Possible PLL Configuration Modes

............................................................................................ 52

3-18

F281x and C281x Low-Power Modes

......................................................................................... 54

4-1

CPU-Timers 0, 1, 2 Configuration and Control Registers

................................................................... 57

4-2

Module and Signal Names for EVA and EVB

................................................................................ 58

4-3

EVA Registers

.................................................................................................................... 59

4-4

ADC Registers

.................................................................................................................... 67

4-5

3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs

............................................ 70

4-6

CAN Registers

.................................................................................................................... 72

4-7

McBSP Registers

................................................................................................................. 75

4-8

SCI-A Registers

.................................................................................................................. 78

4-9

SCI-B Registers

.................................................................................................................. 78

4-10

SPI Registers

..................................................................................................................... 81

4-11

GPIO Mux Registers

............................................................................................................. 83

4-12

GPIO Data Registers

............................................................................................................ 84

5-1

TMS320x281x Peripheral Selection Guide

................................................................................... 87

6-1

TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT

............................................................................... 92

6-2

TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT

............................................................................... 93

6-3

Typical Current Consumption by Various Peripherals (at 150 MHz)

...................................................... 96

6-4

Recommended “Low-Dropout Regulators”

.................................................................................... 97

6-5

TMS320F281x and TMS320C281x Clock Table and Nomenclature

.................................................... 101

6-6

Input Clock Frequency

......................................................................................................... 102

6-7

XCLKIN Timing Requirements – PLL Bypassed or Enabled

............................................................. 102

6-8

XCLKIN Timing Requirements – PLL Disabled

............................................................................ 102

6-9

Possible PLL Configuration Modes

........................................................................................... 102

6-10

XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

...................................................... 103

6-11

Reset (XRS) Timing Requirements

.......................................................................................... 103

6-12

IDLE Mode Timing Requirements

........................................................................................... 107

List of Tables

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