TMS320F2812 datasheet(6/170 Pages) TI

6 / 170 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S – APRIL 2001 – REVISED MARCH 2011

www.ti.com

6-21

EVBSOC Timing

................................................................................................................ 112

6-22

External Interrupt Timing

....................................................................................................... 113

6-23

General-Purpose Output Timing

.............................................................................................. 114

6-24

GPIO Input Qualifier – Example Diagram for QUALPRD = 1

............................................................. 115

6-25

General-Purpose Input Timing

................................................................................................ 116

6-26

SPI Master Mode External Timing (Clock Phase = 0)

..................................................................... 118

6-27

SPI Master External Timing (Clock Phase = 1)

............................................................................. 120

6-28

SPI Slave Mode External Timing (Clock Phase = 0)

....................................................................... 122

6-29

SPI Slave Mode External Timing (Clock Phase = 1)

....................................................................... 124

6-30

Relationship Between XTIMCLK and SYSCLKOUT

....................................................................... 128

6-31

Example Read Access

......................................................................................................... 131

6-32

Example Write Access

......................................................................................................... 132

6-33

Example Read With Synchronous XREADY Access

...................................................................... 134

6-34

Example Read With Asynchronous XREADY Access

..................................................................... 135

6-35

Write With Synchronous XREADY Access

.................................................................................. 137

6-36

Write With Asynchronous XREADY Access

................................................................................ 138

6-37

External Interface Hold Waveform

............................................................................................ 140

6-38

XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

.................................................. 141

6-39

ADC Analog Input Impedance Model

........................................................................................ 145

6-40

ADC Power-Up Control Bit Timing

........................................................................................... 145

6-41

Sequential Sampling Mode (Single-Channel) Timing

...................................................................... 146

6-42

Simultaneous Sampling Mode Timing

....................................................................................... 147

6-43

McBSP Receive Timing

........................................................................................................ 151

6-44

McBSP Transmit Timing

....................................................................................................... 151

6-45

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

................................................... 152

6-46

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

................................................... 153

6-47

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

................................................... 154

6-48

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

................................................... 155

List of Figures

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