TMS320F2812 datasheet(37/170 Pages) TI

37 / 170 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S – APRIL 2001 – REVISED MARCH 2011

3.2.14 Oscillator and PLL

The F281x and C281x can be clocked by an external oscillator or by a crystal attached to the on-chip

oscillator circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be

changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power

operation is desired. Refer to Section 6, Electrical Specifications, for timing details. The PLL block can be

set in bypass mode.

3.2.15 Watchdog

The F281x and C281x support a watchdog timer. The user software must regularly reset the watchdog

counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The

watchdog can be disabled if necessary.

3.2.16 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event

managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of

peripherals to be decoupled from increasing CPU clock speeds.

3.2.17 Low-Power Modes

The F281x and C281x devices are fully static CMOS devices. Three low-power modes are provided:

IDLE:

Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only

those peripherals that must function during IDLE are left operating. An enabled interrupt

from an active peripheral will wake the processor from IDLE mode.

STANDBY:

Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals.

Execution begins on the next valid cycle after detection of the interrupt event.

HALT:

Turns off the internal oscillator. This mode basically shuts down the device and places it

in the lowest possible power consumption mode. Only a reset or XNMI can wake the

device from this mode.

3.2.18 Peripheral Frames 0, 1, 2 (PFn)

The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0:

XINTF:

External Interface Configuration Registers (2812 only)

PIE:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash:

Flash Control, Programming, Erase, Verify Registers

Timers:

CPU-Timers 0, 1, 2 Registers

CSM:

Code Security Module KEY Registers

PF1:

eCAN:

eCAN Mailbox and Control Registers

PF2:

SYS:

System Control Registers

GPIO:

GPIO Mux Configuration and Control Registers

EV:

Event Manager (EVA/EVB) Control Registers

McBSP:

McBSP Control and TX/RX Registers

SCI:

Serial Communications Interface (SCI) Control and RX/TX Registers

SPI:

Serial Peripheral Interface (SPI) Control and RX/TX Registers

ADC:

12-Bit ADC Registers

Functional Overview

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