33781 datasheet(17/44 Pages) FREESCALE

17 / 44 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33781

FUNCTIONAL DESCRIPTIONS

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

Figure 10. Block Illustration

The 33781 is controlled by an MCU through the SPI0

interface. It handles the digital and physical layer portions of

a DBUS master node. Four separate DBUS channels are

included. The physical layer uses a two-wire bus with analog

wave-shaped voltage and current signals. Refer to Figure 1.

Major subsystems include the following:

• SPI0 interface and registers to a main MCU

• SPI1 interface and registers to a second MCU

• Four channels of DSI 2.02 protocol state logic

• CRC block for each channel

• Control and status registers

• Four addressable register sets per channel for queuing up

to four commands and data per bus. The addressable

buffer acts as a circular buffer for command writes and

data reads.

• Pseudo Bus Switch from D0H/L to DPH/L

SPI0 AND REGISTERS

This block contains the SPI0 interface logic and the control

and response registers that are written to and read from the

SPI interface.

The IC is an SPI slave-type device, so MOSI0 (Master-

Out-Slave-In) is an input and MISO0 (Master-In-Slave-Out) is

an output. CS0 and SCLK0 are also inputs.

The SPI0 port can handle 2-byte and 4-byte transfers. It

addresses 87 registers. The organization of the registers is

described in the section entitled SPI0 Register and Bit

Descriptions on page 29.

SPI1 AND REGISTERS

The 33781 has a second SPI port (called SPI1) that allows

valid response data from Bus Channel 2 and 3, along with the

slave address, to be read independently by a second MCU.

This block contains the SPI1 interface logic and the response

registers that are read from the SPI1 interface.

The IC is an SPI slave-type device, so MISO1 (Master-In-

Slave-Out) is an output, and CS1 and SCLK1 are inputs. SPI1

does not use the MOSI (Master-Out-Slave-In) pin or function

as it does not receive commands.

The SPI1 port handles only 16-bit transfers. It addresses

eight registers which are read only.

PROTOCOL ENGINE

This block converts the data to be transmitted from the

registers into the DBUS sequences, and converts DBUS

response sequences to data in the registers.

The DBUS transmit protocol uses a return to 1 type data

with a duty cycle determined by the logic state. The protocol

includes Cyclical Redundancy Check (CRC) generation and

validation.

MC33781 - Functional Block Diagram

Supply Voltage

Power Stage

Supply Voltage

2.5V Regulator

Power Stage

CRC Generation and Checking

Clock Generation and Frequency Spreading

Logic and Control

Over-temperature Sensing

SPI0 Registers and State Machine

Over-current Sensing

DBUS Drivers

and Receivers

Pseudo-bus

Logic and Control

VSUP Voltage Monitor

HCAP Charging Circuitry

SPI1 Registers and State Machine

Switches

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