33781 datasheet(32/44 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33781

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DnRnH REGISTERS

These are read/write registers. There are sixteen of these

registers, four for each of the buses, as shown in Table 8.

When written to, the data is the high byte of a 9- to16-bit

command. When read, it is the high byte of a 9- to 16-bit

return on the DBUS. Writing to this register and the low byte

transaction.

The bit assignments are shown in Figure 24. Even if a

short word of 8 bits is selected for this bus (MSn = 1), this

short word length is set at other than 8 bits, this register will

contain the bits above eight, starting with the ninth bit in the

least significant bit position of the register. Unused bit

positions are don’t care values.

Figure 24. DnRnH Data Register Bit Assignments

DnRnL REGISTERS

These are read/write registers. There are sixteen of these

registers, four for each of the buses. When written to, the data

is the low byte of a 16-bit command. When in read, it is the

low byte of a 16-bit return on the DBUS. Writing to this

schedules a DBUS transaction. The bit assignments are

shown in Figure 25

If this address is pointed to by the first SPI0 byte of a SPI

burst transaction, that transaction is ignored.

Figure 25. DnRnL Data Register Bit Assignments

DnRnSTAT REGISTER

There are read-only registers. These registers cover the

status of their associated DnRnH and DnRnl registers. The

values are latched when CS0 is asserted low. Any changes of

status detected by these bits will not update the register until

CS0

is de-asserted. This is done to ensure that partial

updates will not occur. If this address is pointed to by the first

SPI0 byte of a SPI burst transaction, that transaction is

ignored.

The bit assignments are shown in Figure 26.

Figure 26. DnRnSTAT Register Bit Assignments

ER–CRC Error Bit

• 0 = CRC value for the data in the read buffer was

correct.

• 1 = CRC value for the data in the read buffer was not

correct (data not valid).

CRC errors are associated with each receive buffer, so

that each buffer has a bit to indicate whether the data in that

buffer was received correctly. Whenever a received data

value is available in the DnRnH and DnRnL registers, the

associated CRC error status is available at ERn in the

associated DnRnSTAT register. The ER bit is set or cleared

whenever data is written from the DBUS into the DnRnH/L

receive registers. If Channel Thermal Shutdown or Idle and

SIgnal Mode Disable occur, these bits will be reset along with

the other channel register bits.

TE–Transmit Register Empty Bit

• 0 = Transmit buffer not empty.

• 1 = Transmit buffer empty.

This bit indicates that data has been written to the

associated channel register high and/or low, but has not been

read for sending on the DBUS. The bit is set to 0 on the rising

SPI Data Bit

Bit 7

Read/Write

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

SPI Data Bit

Bit 7

Read/Write

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

SPI Data Bit

Bit 7

Read

SDS

RNE

ICL

FIX0

FIX1

Reset

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