поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

33781 датащи(PDF) 9 Page - Freescale Semiconductor, Inc

номер детали 33781
подробное описание детали  Quad DSI 2.02 Master with
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33781 датащи(HTML) 9 Page - Freescale Semiconductor, Inc

Back Button 33781 Datasheet HTML 5Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 6Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 7Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 8Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 9Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 10Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 11Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 12Page - Freescale Semiconductor, Inc 33781 Datasheet HTML 13Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 44 page
background image
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
33781
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75V
≤ VCC ≤ 5.25V, 9.0V ≤ VSUPn ≤ 25V,-40°C ≤ TA ≤ 90°C, unless otherwise
noted. Voltages relative to GND, unless otherwise noted. Typical values noted reflect the approximate mean values of the
parameter at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CLOCK
CLK Periods (System requirement)(10)
Time High
Time Low
Period
tCLKHI
tCLKLO
tCLKPER
75
75
245
–
–
250
–
–
255
ns
CLK Transition (System requirement)(10)
Time for Low-to-High Transition of the CLK Input Signal
Time for High-to-Low Transition of the CLK Input Signal
tCLKLH
tCLKHL
–
–
–
–
100
100
ns
Reset Low Time
tRSTLO
100
–
–
ns
SPI INTERFACE TIMING
SPI Clock Cycle Time
tCYC
100
–
–
ns
SPI Clock High Time
tHI
40
–
–
ns
SPI Clock Low Time
tLO
40
–
–
ns
SPI CSn Lead Time(11)
tLEAD
50
–
–
ns
SPI CSn Lag Time(11)
tLAG
50
–
–
ns
SPI CS0 Time Between Bursts(10)
tCS0HI
80
–
–
ns
SPI CS1 Time Between Bursts(10)
tCS1HI
300
–
–
ns
Data Setup Time
MOSI0 Valid Before SCLK0 Rising Edge(11)
tSU
10
–
–
ns
Data Hold Time
MOSI0 Valid After SCLK0 Rising Edge(11),(10)
tH
10
–
–
ns
Data Valid Time
SCLKn Falling Edge to MISOn Valid, C = 50pF(12)
tV
–
–
25
ns
Output Disable Time
CSn
Rise to MISOn Hi-Z
tDIS
–
–
50
ns
Rise Time (30% VCC to 70% VCC)
(10)
SCLKn, MOSI0
tR
–
–
10
ns
Fall Time (70% VCC to 30% VCC)(10)
SCLKn, MOSI0
tF
–
–
10
ns
Notes
10.
Not measured in production.
11.
SPI signal timing from the production test equipment is programmed to ensure compliance.
12.
Conditions are verified indirectly during test.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com