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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSC8156 датащи(PDF) 58 Page - Freescale Semiconductor, Inc |
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MSC8156 датащи(HTML) 58 Page - Freescale Semiconductor, Inc |
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58 / 68 page  MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 1 Hardware Design Considerations Freescale Semiconductor 58 3.5.1 DDR Memory Related Pins This section discusses the various scenarios that can be used with either of the MSC8156 DDR ports. Note: The signal names in Table 40, Table 41 and Table 42 are generic names for a DDR SDRAM interface. For actual pin names refer to Table 1. 3.5.1.1 DDR Interface Is Not Used Table 40. Connectivity of DDR Related Pins When the DDR Interface Is Not Used Signal Name Pin Connection MDQ[0–63] NC MDQS[7–0] NC MDQS[7–0] NC MA[15–0] NC MCK[0–2] NC MCK[0–2] NC MCS[1–0] NC MDM[7–0] NC MBA[2–0] NC MCAS NC MCKE[1–0] NC MODT[1–0] NC MMDIC[1–0] NC MRAS NC MWE NC MECC[7–0] NC MDM8 NC MDQS8 NC MDQS8 NC MAPAR_OUT NC MAPAR_IN NC MVREF3 NC GVDD1/GVDD23 NC Notes: 1. For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used. 2. If the DDR controller is not used, disable the internal DDR clock by setting the appropriate bit in the System Clock Control Register (SCCR) and put all DDR I/O in sleep mode by setting DRx_GCR[DDRx_DOZE] (for DDR controller x). See the Clocks and General Configuration Registers chapters in the MSC8156 Reference Manual for details. 3. For MSC8156 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8156, connecting these pins to GND increases device power consumption. |
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