IXP45X datasheet(146/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

146

Document Number: 306261-004US

5.6.3.4

Reset Timings

Figure 49.

Reset Timings

Table 81.

Reset Timings Table Parameters

Symbol

Parameter

Min.

Typ.

Max.

Units

Note

TRELEASE_PWRON_RST_N

Minimum time required to hold the PWON_RST_N at logic 0

state after stable power has been applied to the IXP45X/

IXP46X network processors.

2000

TRELEASE_RESET_IN_N

Minimum time required to hold the RESET_IN_N at logic 0

state after PWRON_RST_N has been released to a logic 1

state. The RESET_IN_N signal must be held low when the

PWRON_RST_N signal is held low.

TPLL_LOCK

Maximum time for PLL_LOCK signal to drive to logic 1 after

RESET_IN_N is driven to logic 1 state. The boot sequence

does not occur until this period is complete.

µs

TEX_ADDR_SETUP

Minimum time for the EX_ADDR signals to drive the inputs

prior to RESET_IN_N being driven to logic 1 state. This is

used for sampling configuration information.

TEX_ADDR_HOLD

Minimum/maximum time for the EX_ADDR signals to drive

the inputs prior to PLL_LOCK being driven to logic 1 state.

This is used for sampling configuration information.

020

TWARM_RESET

Minimum time required to drive RESET_IN_N signal to logic

0 in order to cause a Warm Reset in the IXP45X/IXP46X

network processors. During this period, the power supply

must not be disturbed and PWRON_RST_N signal must

remain at logic high during the entire process.

500

Notes:

TRELEASE_PWRON_RST_N is the time required for the internal oscillator to reach stability.

The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a programmable-logic

device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be active until PLL_LOCK is active.

VCCP

VCCM

VCC

PLL_LOCK

PWRON_RESET_N

RESET_IN_N

EX_ADDR[24:0]

EX_ADDR[24:0]-Pull Up/Down

CFG Settings To Be Captured

IXP46X Drives Outputs

TRELEASE_PWRON_RST_N

TEX_ADDR_SETUP

TRELEASE_RST_N

TPLL_LOCK

TEX_ADDR_HOLD

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