IXP45X datasheet(145/148 Pages) INTEL

145 / 148 page

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

145

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

• Followed by proper resetting of PWRON_RST_N and RESET_IN_N signals as

described in Section 5.6.3.4, “Reset Timings” on page 146

The following procedural sequence must be followed to achieve a successful cold reset:

1. VCC and VCC33 power supplies must reach steady state

2. Hold PWRON_RST_N and RESET_IN_N asserted for 2000nSec

3. De-assert PWRON_RST_N (signal goes high with the help of a pull-up resistor)

4. Continue to hold RESET_IN_N asserted for at least 10nSec more after releasing

PWRON_RST_N

5. De-assert RESET_IN_N (signal goes high with the help of a pull-up resistor)

6. The network processor asserts PLL_LOCK indicating that the processor has

successfully come out of Reset

5.6.3.2

Hardware Warm Reset

A Hardware Warm Reset can only be asserted when PWRON_RST_N is de-asserted and

the network processor is in a normal operating mode. A Hardware Warm Reset is

initiated by the assertion of RESET_IN_N. During this state, all internal registers and

modules are set to their initial default state except for the PLL internal modules. Since

the PLL modules are not reset, the Reset sequence is executed much faster by the

processor.

The following procedural sequence must be followed to achieve a successful Warm

Reset:

1. The system must have previously completed a Cold Reset successfully.

2. PWRON_RST_N must be de-asserted (held high for the entire process).

3. Hold RESET_IN_N asserted for 500nSec.

4. De-assert RESET_IN_N (signal goes high with the help of a pull-up resistor)

5. The network processor asserts PLL_LOCK indicating that the processor has

successfully come out of reset.

5.6.3.3

Soft Reset

A Soft Reset condition is accomplished by the usage of the hardware Watch-Dog Timer

module, and software to manage and perform counter updates. For a complete

description of Watch-Dog Timer functionality, refer to Watchdog Timer Operation sub-

section in the Operating System Timer Chapter of the Intel® IXP45X and Intel® IXP46X

Product Line of Network Processors Developer’s Manual.

The Soft Reset is similar to what is described in Section 5.6.3.2. The main difference is

that there is no hardware requirement; everything is done within the network

processor and software support. That is why it is also referred to as a Soft Warm Reset.

Since Hardware Warm Reset and Soft Reset are very similar, there must be a way to

determine which reset was last executed after recovering. This is done by reading the

Timer Status Register bit 4 (Warm Reset). If this bit was last set to 1, it will indicate

that a Soft Reset was executed, and if the bit was last reset to 0, then it will indicate

that the processor has just come out of either a Hardware Warm Reset or a Cold Reset.

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