IXP45X datasheet(140/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

140

Document Number: 306261-004US

5.6.2.9

I2C Interface Timing

Table 77.

Serial Peripheral Port Interface Timing Values

Symbol

Parameter

Min.

Max.

Units Notes

TPER_INTCLK

Minimum and maximum clock periods which can

be produced by the SSP_SCLK when the clock is

being generated from the internal 3.7033MHz

clock.

.0072

1.8432

MHz

TPER_EXTCLK

Minimum and maximum clock period which can be

produced by the SSP_SCLK when the clock is being

generated from the externally supplied maximum

clock rate of 33 MHz clock (SSP_EXTCLK).

.06445

16.5

MHz

TIS

Input Setup time for data prior to the valid edge of

SSP_SCLK. These signals include SSP_SRXD.

TIH

Input hold time for data after the to the valid edge

of SSP_SCLK. These signals include SSP_SRXD.

0ns

TDOV

SSP_SCLK clock to output valid delay from output

signals. These signals include SSP_STXD and

SSP_SFRM.

TDOH

Output data hold valid from valid edge of

SSP_SCLK. These signals include SSP_STXD and

SSP_SFRM.

1ns

TOV

Output Valid Delay from SSP_EXTCLK to SSP_SCLK

in external clock mode

215

Timing was designed for a system load between 5pF and 40pF

Clock jitter on the SSPSCLK is designed to be an average of the specified clock frequency. The

SSPSCLK jitter specification is unspecified.

Figure 45.

I2C Interface Timing

Table 78.

I2C Interface Timing Values (Sheet 1 of 2)

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Notes

FSCL

SCL Clock Frequency

100

400

KHz

TBUF

Bus Free Time Between STOP and START

Condition

4.7

1.3

μs

THDSTA

Hold Time (repeated) START Condition

0.6

μs

TLOW

SCL Clock Low Time

4.7

1.3

μs

THIGH

SCL Clock High Time

0.6

μs

TSUSTA

Setup Time for a Repeated START Condition

4.7

0.6

μs

THDDAT

Data Hold Time

3.45

0.9

μs

TSUDAT

Data Setup Time

250

100

Notes:

Not tested

After this period, the first clock pulse is generated

Cb = capacitance of one bus line in pF.

I2C_SDA

I2C_SCL

Stop

Start

Repeated

Start

Stop

BUF

LOW

HDSTA

HDDAT

HIIGH

SUDAT

SUSTA

HDSTA

SUSTO

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