IXP45X datasheet(143/148 Pages) INTEL

143 / 148 page

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

143

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

5.6.2.11

JTAG

Table 79.

High-Speed, Serial Timing Values

Symbol

Parameter

Min.

Max.

Units

Notes

Setup time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA prior to the rising edge of clock

5ns

1, 2, 3

Hold time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA after the rising edge of clock

0ns

1, 2, 3

Setup time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA prior to the falling edge of clock

5ns

1, 2, 3

Hold time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA after the falling edge of clock

0ns

1, 2, 3

Rising edge of clock to output delay for HSS_TXFRAME,

HSS_RXFRAME, and HSS_TXDATA

1, 4

Falling edge of clock to output delay for HSS_TXFRAME,

HSS_RXFRAME, and HSS_TXDATA

1, 3, 4

Output Hold Delay after rising edge of final clock for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

0ns

1, 3, 4

Output Hold Delay after falling edge of final clock for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

0ns

1, 3, 4

HSS_TXCLK period and HSS_RXCLK period

1/8.192 MHz 1/512 KHz

Notes:

HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the

IXP45X/IXP46X network processors. The signals are shown to be synchronous for illustrative purposes and

are not required to be synchronous.

Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source as

inputs into the IXP45X/IXP46X network processors. Always applicable to HSS_RXDATA.

The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of the

given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK and

HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.

Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP45X/IXP46X

network processors to an external source. Always applicable to HSS_TXDATA.

The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP45X/IXP46X

network processors. The slowest clock speed that can be accepted or driven is 512 KHz. The maximum

clock speed that can be accepted or driven is 8.192 MHz. The clock duty cycle accepted will be 50/50 +

20%.

Timing was designed for a system load between 5 pF and 30 pF for high drive setting

Figure 47.

Boundary-Scan General Timings

B0416-01

Tbsel

Tbsis

Tbsih

Tbsch

JTG_TCK

JTG_TMS, JTG_TDI

JTG_TDO

Tbsoh

Tbsod

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