IXP45X datasheet(138/148 Pages) INTEL

138 / 148 page

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

138

Document Number: 306261-004US

5.6.2.7.3

Using I/O Wait

The EX_IOWAIT_N signal is available to be shared by devices attached to chip selects 0

through 7, when configured in Intel or Motorola modes of operation. The main purpose

of this signal is to properly communicate with slower devices requiring more time to

respond during data access. During idle cycles, the board is responsible for ensuring

that EX_IOWAIT_N is pulled-up. The Expansion bus controller will always ignore

EX_IOWAIT_N for synchronous Intel mode writes.

For details, see the Intel® IXP45X and Intel® IXP46X Product Line of Network

Processors Developer’s Manual, in the Expansion Bus Controller chapter’s “Using I/O

Wait” section.

Figure 42.

I/O Wait Normal Phase Timing

Note:

Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last

three clock cycles. The data is returned from the peripheral device prior to the three clocks and the

peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though

the strobe phase was configured to pulse for three clocks.

EX_CLK

EX_CS_N[0]

EX_ADDR[23:0]

EX_RD_N

EX_DATA[15:0]

Valid Data

Valid Address

1 Cycle

3 Cycles

1 Cycle

T1=0 h

T2=0 h

T3=2h or 1h or 0h

T4=0 h

T5=0 h

EX_IOWAIT_N

B5242-01

1 Cycle

2 Cycles

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