360J datasheet(60/68 Pages) INTEL

60 / 68 page

Package Mechanical Specifications and Pin Information

Datasheet

PWRGOOD

Input

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and power

supplies are stable and within their specifications. Clean implies that

the signal will remain low (capable of sinking leakage current),

without glitches, from the time that the power supplies are turned on

until they come within specification. The signal must then transition

monotonically to a high state.

The PWRGOOD signal must be supplied to the processor; it is used to

protect internal circuits against voltage sequencing issues. It should

be driven high throughout boundary scan operation.

REQ[4:0]#

Input/

Output

REQ[4:0]# (Request Command) must connect the appropriate pins

of both FSB agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are source

synchronous to ADSTB[0]#.

RESET#

Input

Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at least

two milliseconds after VCC and BCLK have reached their proper

specifications. On observing active RESET#, both FSB agents will

deassert their outputs within two clocks. All processor straps must be

valid within the specified setup time before RESET# is deasserted.

RS[2:0]#

Input

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and

must connect the appropriate pins of both FSB agents.

RSVD

Reserved

/No

Connect

These pins are RESERVED and must be left unconnected on the

board. However, it is recommended that routing channels to these

pins on the board be kept open for possible future use.

SLP#

Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the

processor to enter the Sleep state. During Sleep state, the processor

stops providing internal clock signals to all units, leaving only the

Phase-Locked Loop (PLL) still operating. Processors in this state will

not recognize snoops or interrupts. The processor will recognize only

assertion of the RESET# signal, deassertion of SLP#, and removal of

the BCLK input while in Sleep state. If SLP# is deasserted, the

processor exits Sleep state and returns to Stop-Grant state,

restarting its internal clock signals to the bus and processor core

units. If DPSLP# is asserted while in the Sleep state, the processor

will exit the Sleep state and transition to the Deep Sleep state.

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt, the

processor saves the current state and enter System Management

mode (SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor

will tristate its outputs.

Table 16.

Signal Description (Sheet 6 of 8)

Name

Type

Description

360J датащи(PDF) 60 Page - Intel Corporation

360J датащи(HTML) 60 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

датащи скачать

ссылки URL