360J datasheet(18/68 Pages) INTEL

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Electrical Specifications

Datasheet

NOTES:

BPM[2:0}# and PRDY# are AGTL+ output only signals.

In processor systems where there is no debug port implemented on the system board, these signals are

used to support a debug port interposer. In systems with the debug port implemented on the system

board, these signals are no connects.

Table 2.

FSB Pin Groups

Signal Group

Type

Signals

AGTL+ Common Clock Input

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, DPWR#, PREQ#, RESET#,

RS[2:0]#, TRDY#

AGTL+ Common Clock I/O

Synchronous to

BCLK[1:0]

ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#,

HIT#, HITM#, LOCK#, PRDY#

AGTL+ Source Synchronous I/O

Synchronous to

assoc. strobe

AGTL+ Strobes

Synchronous to

BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS Input

Asynchronous

A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Open Drain Output

Asynchronous

FERR#, IERR#, PROCHOT#, THERMTRIP#

CMOS Output

Asynchronous

PSI#, VID[5:0], BSEL[1:0]

CMOS Input

Synchronous to TCK

TCK, TDI, TMS, TRST#

Open Drain Output

Synchronous to TCK

TDO

FSB Clock

Clock

BCLK[1:0], ITP_CLK[1:0]2

Power/Other

COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,

THERMDA, THERMDC, VCC, VCCA[3:0], VCCP,

VCCQ[1:0], VCC_SENSE, VSS, VSS_SENSE

Signals

Associated Strobe

REQ[4:0]#,

A[16:3]#

ADSTB[0]#

A[31:17]#

ADSTB[1]#

D[15:0]#, DINV0#

DSTBP0#, DSTBN0#

D[31:16]#, DINV1# DSTBP1#, DSTBN1#

D[47:32]#, DINV2# DSTBP2#, DSTBN2#

D[63:48]#, DINV3# DSTBP3#, DSTBN3#

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