360J datasheet(11/68 Pages) INTEL

11 / 68 page

Datasheet

Low Power Features

2.1

Clock Control and Low Power States

The Celeron M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep

Sleep states for optimal power management. See Figure 1 for a visual representation of

the processor low-power states.

2.1.1

Normal State

This is the normal operating state for the processor.

2.1.2

AutoHALT Power-Down State

AutoHALT Power-Down is a low-power state entered when the processor executes the

HALT instruction. The processor will transition to the Normal state upon the occurrence

of SMI#,INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause

the processor to immediately initialize itself.

The system can generate a STPCLK# while the processor is in the AutoHALT Power-

Down state. When the system deasserts the STPCLK# interrupt, the processor will

return execution to the HALT state. While in AutoHALT Power-Down state, the processor

will process bus snoops and interrupts.

2.1.3

Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20

bus clocks after the response phase of the processor issued Stop-Grant Acknowledge

special bus cycle.

Figure 1.

Clock Control States

snoop

occurs

Stop

Grant

Normal

Sleep

HALT/

Grant

Snoop

Auto Halt

Deep

Sleep

STPCLK# asserted

SLP# asserted

SLP# deasserted

STPCLK# deasserted

snoop

serviced

HLT

instruction

snoop

serviced

snoop

occurs

DPSLP#

de-asserted

DPSLP#

asserted

STPCLK#

asserted

STPCLK#

deasserted

halt

break

V0001-04

Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

360J датащи(PDF) 11 Page - Intel Corporation

360J датащи(HTML) 11 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

датащи скачать

ссылки URL