PCA2000_2001

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Product data sheet

Rev. 08 — 23 August 2010

9 of 30

NXP Semiconductors

PCA2000; PCA2001

32 kHz watch circuit with programmable adaptive motor pulse

[1]

Including the highest driving stage, which one has no motor step detection.

[2]

If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the

second highest level must be smaller than the highest driving level.

Table 5.

Description of word A bits

Bit

Value

Description

Inhibition time

1 to 7

-

adjust the number of the 8192 Hz pulses to be removed;

bit 1 is the MSB and bit 7 is the LSB

Calibration period

80

1 minute

12 minutes

Table 6.

Description of word B bits

Bit

Value

Description

Duty cycle lowest driving stage

1to2

00

37.5 %

01

43.75 %

10

50 %

11

56.25 %

Number of driving stages

3to4

00

3

01

4

10

5

11

6[1]

Duty cycle highest driving stage

50

75 %[2]

1100 %

Pulse stretching

6

0

no pulse stretching

1

pulse of 2

× t

Factory test bits

7to8

-

-