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ISL6334DIRZ датащи(PDF) 24 Page - Intersil Corporation |
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ISL6334DIRZ датащи(HTML) 24 Page - Intersil Corporation |
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24 / 28 page ![]() 24 FN6802.2 August 31, 2010 the power stage, since the DC resistance of the current sense element may be changed according to the operational temperature. RX in Equation 27 should be the maximum DC resistance of the current sense element at the all operational temperature. In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistors. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section entitled “Voltage Regulation” on page 13). Choose RISEN,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase, as shown in Equation 28: In Equation 28, make sure that ΔT2 is the desired temperature rise above the ambient temperature, and ΔT1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 28 is usually sufficient, it may occasionally be necessary to adjust RISEN two or more times to achieve optimal thermal balance between all channels. Compensation The ISL6334D converter can be accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 17, provides the necessary compensation. The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type III compensator has an extra high-frequency pole, fHF. This pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose fHF = 10f0, but it can be higher if desired. Choosing fHF to be lower than 10f0 can cause problems with too much phase shift below the system bandwidth. In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 29, RFB can be arbitrarily chosen as 1kΩ to 2kΩ. The remaining compensation components are then selected. In Equation 29, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VP-P is the peak-to-peak sawtooth signal amplitude, typically 1.5V. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, ΔVMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final RISEN 2, RISEN ΔT 2 ΔT 1 ---------- = (EQ. 28) FIGURE 17. COMPENSATION CIRCUIT ISL6333 COMP CC RC RFB FB VSEN C2 C1 R1 CC VIN 2 π fHF LC ⋅ 1 – ⋅⋅ ⋅ () ⋅ 2 π ⋅ ()2 f 0 fHF LC ⋅ () R FB VP-P ⋅⋅ ⋅ ⋅ ⋅ ----------------------------------------------------------------------------------------------------- = RC VPP 2π ⎝⎠ ⎛⎞ ⋅ 2 f0 fHF LCRFB ⋅⋅ ⋅ ⋅ ⋅ VIN 2 π fHF LC ⋅ 1 – ⋅⋅ ⋅ () ⋅ ----------------------------------------------------------------------------------------- = R1 RFB CESR ⋅ LC ⋅ C ESR ⋅ – -------------------------------------------- ⋅ = C1 LC ⋅ C ESR ⋅ – RFB -------------------------------------------- = C2 VIN 2 π ⋅ ()2 f 0 fHF LC ⋅ () R FB VP-P ⋅⋅ ⋅ ⋅ ⋅ ----------------------------------------------------------------------------------------------------- = (EQ. 29) ISL6334D |
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