ISL6334DIRZ datasheet(18/28 Pages) INTERSIL

18 / 28 page

FN6802.2

August 31, 2010

Soft-Start

ISL6334D based VR has 4 periods during soft-start, as shown

in Figure 9. After VCC, EN_VTT and EN_PWR reach their

POR/enable thresholds, the controller will have a fixed delay

period tD1. After this delay period, the VR will begin first

soft-start ramp until the output voltage reaches 1.1V VBOOT

voltage. Then, the controller will regulate the VR voltage at 1.1V

for another fixed period tD3. At the end of tD3 period, ISL6334D

reads the VID signals. If the VID code is valid, ISL6334D will

initiate the second soft-start ramp until the voltage reaches the

VID voltage minus offset voltage.

The soft-start time is the sum of the 4 periods, as shown in

Equation 11.

tD1 is a fixed delay with the typical value as 1.36ms. tD3 is

determined by the fixed 85µs plus the time to obtain valid

VID voltage. If the VID is valid before the output reaches the

1.1V, the minimum time to validate the VID input is 500ns.

Therefore, the minimum tD3 is about 86µs.

During tD2 and tD4, ISL6334D digitally controls the DAC

voltage change at 6.25mV per step. The time for each step is

determined by the frequency of the soft-start oscillator, which

is defined by the resistor RSS from SS pin to GND. The

second soft-start ramp time tD2 and tD4 can be calculated

based on Equations 12 and 13:

For example, when VID is set to 1.5V and the RSS is set at

100k

Ω, the first soft-start ramp time tD2 will be 704µs and the

second soft-start ramp time tD4 will be 256µs.

After the DAC voltage reaches the final VID setting,

VR_RDY will be set to high with the fixed delay tD5. The

typical value for tD5 is 85µs. Before the VR_RDY is

released, the controller disregards the PSI# input and

always operates in normal CCM PWM mode.

Current Sense Output

The current flowing out of the IMON pin is equal to the

sensed average current inside ISL6334D. In typical

applications, a resistor is placed from the IMON pin to GND

to generate a voltage, which is proportional to the load

current and the resistor value, as shown in Equation 14:

where VIMON is the voltage at the IMON pin, RIOUT is the

resistor between the IMON pin and GND, ILOAD is the total

output current of the converter, RISEN is the sense resistor

connected to the ISEN+ pin, N is the active channel number,

and RX is the DC resistance of the current sense element,

either the DCR of the inductor or RSENSE depending on the

sensing method.

The resistor from the IMON pin to GND should be chosen to

ensure that the voltage at the IMON pin is less than 1.11V

under the maximum load current. If the IMON pin voltage is

higher than 1.11V, overcurrent shutdown will be triggered, as

described in “Overcurrent Protection” on page 19.

A small capacitor can be placed between the IMON pin and

GND to reduce the noise impact. If this pin is not used, tie it

to GND.

FIGURE 8. POWER SEQUENCING USING THRESHOLD

SENSITIVE ENABLE (EN) FUNCTION

0.875V

EXTERNAL CIRCUIT

ISL6334D INTERNAL CIRCUIT

EN_PWR

+12V

POR

CIRCUIT

100k

9.1k

ENABLE

COMPARATOR

SOFT-START

AND

FAULT LOGIC

EN_VTT

VCC

0.875V

tSS

tD1 tD2 tD3 tD4

(EQ. 11)

tD2

1.1xRSS

6.25x25

------------------------

μs

()

(EQ. 12)

tD4

VVID 1.1

–

()xR

6.25x25

------------------------------------------------

μs

()

(EQ. 13)

FIGURE 9. SOFT-START WAVEFORMS

VOUT, 500mV/DIV

EN_VTT

500µs/DIV

tD3 tD4 tD5

VR_RDY

tD1

tD2

VIMON

RIOUT

-------------------

RISEN

------------------ILOAD

(EQ. 14)

ISL6334D

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