AT90PWM3 datasheet(110/361 Pages) ATMEL

110 / 361 page

110

4317J–AVR–08/10

AT90PWM2/3/2B/3B

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 104.

15.5.1

Input Capture Trigger Source

The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B).

Be aware that changing trigger source can trigger a capture. The Input Capture Flag must there-

fore be cleared after the change.

The Input Capture pin (ICPn) IS sampled using the same technique as for the Tn pin (Figure 13-

1 on page 82). The edge detector is also identical. However, when the noise canceler is

enabled, additional logic is inserted before the edge detector, which increases the delay by four

system clock cycles. Note that the input of the noise canceler and edge detector is always

enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to

define TOP.

An Input Capture can be triggered by software by controlling the port of the ICPn pin.

15.5.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in

Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICRn Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

15.5.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICRn Register before the next event occurs, the ICRn will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICRn

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICFn Flag is not required (if an interrupt handler is used).

15.6

Output Compare Units

The 16-bit comparator continuously compares TCNTn with the Output Compare Register

(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output

Compare Flag (OCFnx) at the next “timer clock cycle”. If enabled (OCIEnx = 1), the Output Com-

pare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared

when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ-

AT90PWM3 датащи(PDF) 110 Page - ATMEL Corporation

AT90PWM3 датащи(HTML) 110 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL