AT90PWM3 datasheet(20/361 Pages) ATMEL

20 / 361 page

4317J–AVR–08/10

AT90PWM2/3/2B/3B

Figure 3. On-chip Data SRAM Access Cycles

6.3

EEPROM Data Memory

The AT90PWM2/2B/3/3B contains 512 bytes of data EEPROM memory. It is organized as a

separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

For a detailed description of SPI and Parallel data downloading to the EEPROM, see “Serial

Downloading” on page 293, and “Parallel Programming Parameters, Pin Mapping, and Com-

mands” on page 282 respectively.

6.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 6-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V

CC is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

For details on how to avoid problems in these situations seeSee “Preventing EEPROM Corrup-

tion” on page 25.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

6.3.2

The EEPROM Address Registers – EEARH and EEARL

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

Bit

15141312

–

EEAR8

EEARH

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