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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT90PWM3 датащи(PDF) 7 Page - ATMEL Corporation |
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AT90PWM3 датащи(HTML) 7 Page - ATMEL Corporation |
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7 / 361 page  7 4317J–AVR–08/10 AT90PWM2/3/2B/3B 4.1 Block Diagram Figure 4-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex- ible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11- channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. 8Kx8 Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM 512 bytes Data Bus 8-bit Data SRAM 512 bytes Interrupt Unit SPI Unit Watchdog Timer 3 Analog Comparators DAC ADC PSC 2/1/0 Timer 1 Timer 0 DALI USART |
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