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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MC68HC705P9CS датащи(PDF) 97 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS датащи(HTML) 97 Page - Freescale Semiconductor, Inc |
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97 / 160 page  Computer Operating Properly Watchdog (COP) Interrupts MC68HC705P9 — Rev. 4.0 Technical Data MOTOROLA Computer Operating Properly Watchdog (COP) 97 8.4.3 Clearing the COP Watchdog To clear the COP watchdog and prevent a COP reset, write a logic zero to bit 0 (COPC) of the COP register at location $1FF0. If the main program executes within the COP timeout period, the clearing routine needs to be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once. NOTE: Place the clearing routine in the main program and not in an interrupt routine. Clearing the COP watchdog in an interrupt routine might prevent COP watchdog timeouts even though the main program is not operating properly. 8.5 Interrupts The COP watchdog does not generate interrupts. 8.6 COP Register The COP register is a write-only register that returns the contents of EPROM location $1FF0 when read. COPC — COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. $1FF0 Bit 7 6 54321 Bit 0 Read: D7 D6 D5 D4 D3 D2 D1 D0 Write: COPC Reset: UUUUUUU 0 = Unimplemented U = Unaffected Figure 8-1. COP Register (COPR) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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