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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MC68HC705P9CS датащи(PDF) 67 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS датащи(HTML) 67 Page - Freescale Semiconductor, Inc |
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67 / 160 page  Resets and Interrupts Resets MC68HC705P9 — Rev. 4.0 Technical Data MOTOROLA Resets and Interrupts 67 Figure 5-2. Power-On Reset Timing 5.2.2 External Reset A logic zero applied to the RESET pin for one and one-half t CYC generates an external reset. A Schmitt trigger senses the logic level at the RESET pin. Figure 5-3. External Reset Timing 1FFE 4064 tCYC VDD OSC1 PIN INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: INTERNAL DATA BUS 1FFE 1FFE 1FFE 1FFE 1FFE 1FFF (NOTE 1) 1. Power-on reset threshold is typically between 1 V and 2 V. 2. Internal clock, internal address bus, and internal data bus are not available externally. NEW PCH NEW PCL Table 5-1. External Reset Timing Characteristic Symbol Min Max Unit RESET Pulse Width tRL 1.5 — tCYC INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: INTERNAL DATA BUS 1FFE 1FFE 1FFE 1FFE 1FFF NEW PC 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. NEW PCH tRL NEW PC NEW PCL DUMMY OP CODE RESET Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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