MC68HC705P9CS datasheet(52/160 Pages) FREESCALE

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Central Processor Unit (CPU)

Technical Data

MC68HC705P9 — Rev. 4.0

Central Processor Unit (CPU)

MOTOROLA

4.7.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access

data with variable addresses at any location in memory. The CPU adds

the unsigned byte in the index register to the two unsigned bytes

following the opcode. The sum is the effective address of the operand.

The first byte after the opcode is the high byte of the 16-bit offset; the

second byte is the low byte of the offset.

Indexed, 16-bit offset instructions are useful for selecting the kth element

in an n-element table anywhere in memory.

As with direct and extended addressing, the Motorola assembler

determines the shortest form of indexed addressing.

4.7.1.8 Relative

Relative addressing is only for branch instructions. If the branch

condition is true, the CPU finds the effective branch destination by

adding the signed byte following the opcode to the contents of the

program counter. If the branch condition is not true, the CPU goes to the

next instruction. The offset is a signed, two’s complement byte that gives

a branching range of –128 to +127 bytes from the address of the next

location after the branch instruction.

When using the Motorola assembler, the programmer does not need to

calculate the offset, because the assembler determines the proper offset

and verifies that it is within the span of the branch.

4.7.2 Instruction Types

The MCU instructions fall into the following five categories:

•

Read-Modify-Write Instructions

•

Jump/Branch Instructions

•

Bit Manipulation Instructions

•

Control Instructions

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