ADS5400IPZP datasheet(22/50 Pages) TI

22 / 50 page

ADS5400

SLAS611B – OCT 2009 – REVISED MARCH 2010

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set to 1 if writing this register

BIT <6>

Powerdown

device active

device in low power mode (sleep mode)

BIT <7>

Temperature Sensor

temperature sensor inactive

temperature sensor active, independent of powerdown bit in Bit<6>,

allows reading of temp sensor while the rest of the ADC is in sleep

mode

Table 12. Serial Register 0x06 (Read or Write)

Address (hex)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x06

Data output mode

LVDS termination

LVDS current

Force LVDS outputs

Defaults

BIT <0:1>

Force LVDS outputs

00 and 01

normal operating mode (LVDS is outputting sampled data bits)

forces the LVDS outputs to all logic zeros (data and clock out) - for

level check

forces the LVDS outputs to all logic ones (data and clock out) - for

level check

BIT <3:2>

Set LVDS output current

2.5mA

3.5mA (default)

4.5mA

5.5mA

BIT <5:4>

Set Internal LVDS termination differential resistor (for LVDS

outputs only)

00 and 01

no internal termination

internal 200

Ω resistor selected

internal 100

Ω resistor selected

BIT <7:6>

Control Data Output Mode

normal mode (LVDS is outputting sampled data bits)

scrambled output mode (D11:D1 is XOR'd with D0)

output data is replaced with PRBS test pattern (7-bit sequence)

output data is replaced with toggling test pattern (all 1s, then all 0s,

then all 1s, etc.....on all bits)

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