ADS5400IPZP datasheet(36/50 Pages) TI

36 / 50 page

ADC

TI ADS5400

CLKIN

VCO

REF

CDC

(ClockDistributionChip)

Ex : TICDCM7005

LVPECL

LVCMOS

1000 MHz (To TransmitDAC )

125 MHz (ToDSP )

250 MHz (ToFPGA )

ToOther

BoardMaster

ReferenceClock

( HighorLowJitter)

10 MHz

1000 MHz

LowJitterOscillator

SAW

LVPECL

XFMR

AMP

Thisisageneralblockdiagramexample: ConsultthedatasheetoftheCDCM7005 forproperschematic

andforspecificationsregardingallowableinputandoutputfrequencyandamplituderanges .

AMP and /orBPFoptional , dependingonjitterrequirements

LowJitterClockDistribution

ADS5400

SLAS611B – OCT 2009 – REVISED MARCH 2010

www.ti.com

Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the

clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.

For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not

required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see

Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC

Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the

jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the

insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is

too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF.

Figure 37 represents a scenario where an LVPECL output is used from a TI CDCM7005 with the clock signal

path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult to estimate and

requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of

insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC

is still not adequate. The total jitter at the CDCM7005 output depends heavily on the phase noise of the VCXO

selected. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further

conditioning, it is possible to clock the ADS5400 directly from the CDCM7005 using differential LVPECL outputs

(see the CDCM7005 data sheet for the exact schematic). A careful analysis of the required jitter and of the

components involved is recommended before determining the proper approach.

Figure 37. Clock Source Diagram

Product Folder Link(s): ADS5400

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