ADS5400IPZP datasheet(37/50 Pages) TI

37 / 50 page

ADS5400

www.ti.com

SLAS611B – OCT 2009 – REVISED MARCH 2010

Digital Outputs

Output Bus and Clock Options

The ADS5400 has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In

single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock

rate on A and B. While in single bus mode, CLKOUTA will be at frequency CLKIN/2 and a DDR interface is

achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing

options for an SDR or DDR interface. The ADC provides 12 LVDS-compatible data outputs (D11 to D0; D11 is

the MSB and D0 is the LSB), a data-ready signal (CLKOUT), and an over-range indicator (OVR) on each bus. It

is recommended to use the CLKOUT signal to capture the output data of the ADS5400. Both two's complement

and offset binary are available output formats, in register 0x05.

The capacitive loading on the digital outputs should be minimized. Higher capacitance shortens the data-valid

timing window. The values given for timing were obtained with an estimated 3.5-pF of differential parasitic board

capacitance on each LVDS pair.

Reset and Synchronization

Referencing the timing diagrams starting in Figure 1, the polarity of CLKOUT with respect to the sample N data

output transition is undetermined because of the unknown startup logic level of the clock divider that generates

the CLKOUT signal, whether in frequency CLKIN/2 or CLKIN/4 mode. The polarity of CLKOUT could invert when

power is cycled off/on. If a defined CLKOUT polarity is required, the RESET input pins are used to reset the

clock divider to a known state after power on with a reset pulse. A RESET is not commonly required when using

only one ADS5400 because a one sample uncertainty at startup is not usually a problem.

NOTE: initial samples capture RESET = HIGH on the rising edge of CLKINP. This is being corrected for final

samples and will reflect the diagram as drawn, with RESET = HIGH captured on falling edge of CLKINP.

In addition to CLKOUT alignment using RESET, a synchronization mode is provided in register 0x05. In this

mode, the OVR output becomes the SYNCOUT. The SYNCOUT will indicate which sample was present when

the RESET input pulse was captured in a HIGH state. The OVR indicator is not available when sync mode is

enabled. In single bus mode, only SYNCOUTA is used. In dual bus mode, only SYNCOUTB is used.

LVDS

Differential source loads of 100

Ω and 200Ω are provided internal to the ADS5400 and can be implemented using

of 2.5, 4.5, and 5.5mA are provided to save power or improve the LVDS signal quality when the environment

provides excessive loading.

Over Range

The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. This

flag is provided as an indicator that the analog input signal exceeded the full-scale input limit set in register 0x00

and 0x01 (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input

signal within acceptable limits. The OVR pins are not available when the sychronization mode is enabled, as they

become the SYNCOUT indicator.

Data Scramble

In normal operation, with this mode disabled, the MSBs have similar energy to the analog input fundamental

frequency and can in some instances cause board interference. A data scramble mode is available in register

0x06. In this mode, bits 11-1 are XOR'd with bit 0 (the LSB). Because of the random nature of the LSB, this has

the effect of randomizing the data pattern. To de-scramble, perform the opposite operation in the digital chip after

receiving the scrambled data.

Product Folder Link(s): ADS5400

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