SPMC68CK338CPV14 datasheet(19/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper

byte of SYNCR. Bits in the lower byte show the status of or control the operation of internal and external

clocks. SYNCR can be read or written only when the CPU is operating in supervisor mode.

W — Frequency Control (VCO)

This bit controls a prescaler tap in the synthesizer feedback loop. Setting it increases the VCO speed

by a factor of four. VCO relock delay is required.

X — Frequency Control (Prescaler)

This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles

the clock speed without changing the VCO speed. No VCO relock delay is required.

Y[5:0] — Frequency Control (Counter)

The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by

a value of Y + 1. Values range from 0 to 63. VCO relock delay is required.

EDIV — E Clock Divide Rate

0 = ECLK frequency is system clock divided by 8.

1 = ECLK frequency is system clock divided by 16.

ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.6 Chip-Selects for more

information.

STCPU — Stop CPU32L Clock on LPSTOP

0 = When LPSTOP is executed, the intermodule bus clock (IMBCLK) is held low. When a trace,

reset exception, or SIML interrupt occurs, the IMBCLK turns back on and the CPU32L begins

executing instructions again.

1 = When LPSTOP is executed, the IMBCLK continues to run but is gated off and held low only

where it enters the CPU32L. When a trace, reset exception, or interrupt from any module oc-

curs, the IMBCLK is gated back on where it enters the CPU32L, and execution begins again.

SLOCK — Synthesizer Lock Flag

0 = VCO has not locked, but is enabled on the desired frequency.

1 = VCO has locked on the desired frequency, or is disabled.

The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock

status until after the user writes to SYNCR.

STSIM — Stop Mode SIML Clock

0 = When LPSTOP is executed, the SIML clock is driven by the crystal oscillator and the VCO is

turned off to conserve power.

1 = When LPSTOP is executed, the SIML clock is driven by the VCO.

STEXT — Stop Mode External Clock

0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.

1 = When LPSTOP is executed, the CLKOUT signal is driven by the SIML clock, as determined by

the state of the STSIM bit.

3.3.4 External MC6800 Bus Clock

The state of the ECLK division rate bit (EDIV) in SYNCR determines clock rate for the ECLK signal avail-

able on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can

be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The

clock is enabled by the CS10 field in chip-select pin assignment register 1 (CSPAR1). ECLK operation

during low-power stop is described in the following paragraph. Refer to 3.6 Chip-Selects for more in-

formation about the external bus clock.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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