SPMC68CK338CPV14 datasheet(27/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

3.5.2 Function Codes

The CPU32L automatically generates function code signals FC[2:0]. The function codes can be consid-

ered address extensions that automatically select one of eight address spaces to which an address ap-

plies. These spaces are designated as either user or supervisor, and program or data spaces. Address

space seven is designated CPU space. CPU space is used for control information not normally associ-

ated with read or write bus cycles. Function codes are valid while AS is asserted. Table 14 displays

CPU32L address space encodings.

3.5.3 Address Bus

Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during

a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is

valid while AS is asserted.

3.5.4 Address Strobe

AS is a timing signal that indicates the validity of an address on the address bus and the validity of many

control signals. It is asserted one-half clock after the beginning of a bus cycle.

3.5.5 Data Bus

Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data

to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During

a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For

a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The

MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.

Table 13 Size Signal Encoding

SIZ1

SIZ0

Transfer Size

Byte

Word

Three Byte

Long Word

Table 14 CPU32L Address Space Encoding

FC2

FC1

FC0

Address Space

Reserved

User Data Space

User Program Space

Reserved

Supervisor Data Space

Supervisor Program Space

CPU Space

Freescale Semiconductor, Inc.

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