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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 621 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 621 Page - Freescale Semiconductor, Inc |
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621 / 1348 page  Chapter 17 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 621 17.3.2.3 Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used only when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see Figure 1-7). CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Figure 17-7. GPAGE Address Mapping Example 17-1. This example demonstrates usage of the GPAGE register LDAADR EQU $5000 ;Initialize LDADDR to the value of $5000 MOVB #$14, GPAGE ;Initialize GPAGE register with the value of $14 GLDAA >LDAADR ;Load Accu A from the global address $14_5000 Address: 0x0010 76543210 R0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 W Reset 00000000 = Unimplemented or Reserved Figure 17-6. Global Page Index Register (GPAGE) Table 17-7. GPAGE Field Descriptions Field Description 6–0 GP[6:0] Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is to be accessed. Bit16 Bit 0 Bit15 Bit22 CPU Address [15:0] GPAGE Register [6:0] Global Address [22:0] |
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