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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 525 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 525 Page - Freescale Semiconductor, Inc |
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525 / 1348 page  Chapter 12 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 525 12.3.2.4 SPI Status Register (SPISR) Read: Anytime Write: Has no effect 76543210 R SPIF 0 SPTEF MODF 0000 W Reset 00100000 = Unimplemented or Reserved Figure 12-6. SPI Status Register (SPISR) Table 12-7. SPISR Field Descriptions Field Description 7 SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 0 Transfer not yet complete. 1 New data copied to SPIDR. 5 SPTEF SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored. 0 SPI data register not empty. 1 SPI data register empty. 4 MODF Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 12.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. |
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