SC312XDP512F0MPVR datasheet(385/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

385

On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.

There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an

edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.

8.4.2.2

PWM Polarity

Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown

on the block diagram as a mux select of either the Q output or the Q output of the PWM output ﬂip ﬂop.

When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the

beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit

is zero, the output starts low and then goes high when the duty count is reached.

8.4.2.3

PWM Period and Duty

Dedicated period and duty registers exist for each channel and are double buffered so that if they change

while the channel is enabled, the change will NOT take effect until one of the following occurs:

•

The effective period ends

•

The counter is written (counter resets to $00)

•

The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period and duty registers will go

directly to the latches as well as the buffer.

A change in duty or period can be forced into effect “immediately” by writing the new value to the duty

and/or period registers and then writing to the counter. This forces the counter to reset and the new duty

and/or period values to be latched. In addition, since the counter is readable, it is possible to know where

the count is with respect to the duty value and software can be used to make adjustments

NOTE

When forcing a new period or duty into effect immediately, an irregular

PWM cycle can occur.

Depending on the polarity bit, the duty registers will contain the count of

either the high time or the low time.

8.4.2.4

PWM Timer Counters

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see

Section 8.4.1, “PWM Clock Select” for the available clock sources and rates). The counter compares to

two registers, a duty register and a period register as shown in Figure 8-19. When the PWM counter

matches the duty register, the output ﬂip-ﬂop changes state, causing the PWM waveform to also change

state. A match between the PWM counter and the period register behaves differently depending on what

output mode is selected as shown in Figure 8-19 and described in Section 8.4.2.5, “Left Aligned Outputs”

and Section 8.4.2.6, “Center Aligned Outputs”.

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