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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

383

Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale

value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the

8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater

range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value

in the PWMSCLA register.

NOTE

Clock SA = Clock A / (2 * PWMSCLA)

When PWMSCLA = $00, PWMSCLA value is considered a full scale value

of 256. Clock A is thus divided by 512.

Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock

SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register.

NOTE

Clock SB = Clock B / (2 * PWMSCLB)

When PWMSCLB = $00, PWMSCLB value is considered a full scale value

of 256. Clock B is thus divided by 512.

As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for

this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this

through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value

of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by

8 rate.

Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.

Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper

rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or

PWMSCLB is written prevents this.

NOTE

Writing to the scale registers while channels are operating can cause

irregularities in the PWM outputs.

8.4.1.3

Clock Select

Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock

choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock

selection is done with the PCLKx control bits in the PWMCLK register.

NOTE

Changing clock control bits while channels are operating can cause

irregularities in the PWM outputs.

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