SC312XDP512F0MPVR datasheet(322/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

322

Freescale Semiconductor

7.3.2.6

Timer System Control Register 1 (TSCR1)

Read or write: Anytime except PRNT bit is write once

All bits reset to zero.

76543210

TEN

TSWAI

TSFRZ

TFFCA

PRNT

000

Reset

00000000

= Unimplemented or Reserved

Figure 7-9. Timer System Control Register 1 (TSCR1)

Table 7-7. TSCR1 Field Descriptions

Field

Description

TEN

Timer Enable

0 Disables the main timer, including the counter. Can be used for reducing power consumption.

1 Allows the timer to function normally.

Note: If for any reason the timer is not active, there is no

÷64 clock for the pulse accumulator since the ÷64 is

generated by the timer prescaler.

TSWAI

Timer Module Stops While in Wait

0 Allows the timer module to continue running during wait.

1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode.

Timer interrupts cannot be used to get the MCU out of wait.

TSFRZ

Timer and Modulus Counter Stop While in Freeze Mode

0 Allows the timer and modulus counter to continue running while in freeze mode.

1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation.

The pulse accumulators do not stop in freeze mode.

TFFCA

Timer Fast Flag Clear All

0 Allows the timer ﬂag clearing to function normally.

1 A read from an input capture or a write to the output compare channel registers causes the corresponding

channel ﬂag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF ﬂag

in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF ﬂags in the

PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF ﬂag in the PBFLG register.

Any access to the MCCNT register clears the MCZF ﬂag in the MCFLG register. This has the advantage of

eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental ﬂag

clearing due to unintended accesses.

Note: The ﬂags cannot be cleared via the normal ﬂag clearing mechanism (writing a one to the ﬂag) when

TFFCA = 1.

PRNT

Precision Timer

0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the

delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection.

MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection.

1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR

prescaler Precision Timer Modulus Counter Prescaler selection.

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