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SC312XDP512F0MPVR датащи(PDF) 325 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 325 Page - Freescale Semiconductor, Inc |
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325 / 1348 page ![]() Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 325 7.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4) Read or write: Anytime All bits reset to zero. 76543210 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W Reset 00000000 Figure 7-13. Timer Control Register 3 (TCTL3) 76543210 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W Reset 00000000 Figure 7-14. Timer Control Register 4 (TCTL4) Table 7-11. TCTL3/TCTL4 Field Descriptions Field Description EDG[7:0]B 7, 5, 3, 1 Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the active edge for the 16-bit pulse accumulator PACB. See Table 7-12. EDG[7:0]A 6, 4, 2, 0 Table 7-12. Edge Detector Circuit Configuration EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) |
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