PIC16F688-ISLASHML datasheet(109/204 Pages) MICROCHIP

109 / 204 page

DS41203E-page 107

PIC16F688

10.4.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Clearing the

CSRC bit of the TXSTA register configures the device as

a slave. Clearing the SREN and CREN bits of the RCSTA

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

10.4.2.1

EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes

are

identical

(see

Section 10.4.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first character will immediately transfer to

the TSR register and transmit.

The second word will remain in TXREG register.

The TXIF bit will not be set.

After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

10.4.2.2

Synchronous Slave Transmission

Set-up:

Set the SYNC and SPEN bits and clear the

CSRC bit.

Clear the CREN and SREN bits.

If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

If 9-bit transmission is desired, set the TX9 bit.

Enable transmission by setting the TXEN bit.

If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

Start

transmission

writing

the

Least

Significant 8 bits to the TXREG register.

TABLE 10-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Value on

POR, BOR

Value on

all other

Resets

BAUDCTL

ABDOVF

RCIDL

—SCKP

BRG16

—

WUE

ABDEN

01-0 0-00

INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF

0000 000x

PIE1

EEIE

ADIE

RCIE

C2IE

C1IE

OSFIE

TXIE

TMR1IE

0000 0000

PIR1

EEIF

ADIF

RCIF

C2IF

C1IF

OSFIF

TXIF

TMR1IF

0000 0000

RCREG

EUSART Receive Data Register

0000 0000

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

SPBRG

BRG7

BRG6

BRG5

BRG4

BRG3

BRG2

BRG1

BRG0

0000 0000

SPBRGH

BRG15

BRG14

BRG13

BRG12

BRG11

BRG10

BRG9

BRG8

0000 0000

TRISC

—

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

--11 1111

TXREG

EUSART Transmit Data Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

0000 0010

Legend:

= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

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