PIC16F688-ISLASHML datasheet(90/204 Pages) MICROCHIP

90 / 204 page

PIC16F688

DS41203E-page 88

10.1.2

EUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode would typically be used in

RS-232 systems. The receiver block diagram is shown

in Figure 10-2. The data is received on the RX/DT pin

and drives the data recovery block. The data recovery

block is actually a high-speed shifter operating at 16

times the baud rate, whereas the serial Receive Shift

bits of the character have been shifted in, they are

immediately transferred to a two character First-In-

First-Out (FIFO) memory. The FIFO buffering allows

reception of two complete characters and the start of a

third character before software must start servicing the

EUSART receiver. The FIFO and RSR registers are not

directly accessible by software. Access to the received

data is via the RCREG register.

10.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA

enables

the

EUSART

and

automatically configures the RX/DT I/O pin as an input.

If the RX/DT pin is shared with an analog peripheral the

analog I/O function must be disabled by clearing the

corresponding ANSEL bit.

10.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 10.1.2.4 “Receive Framing

Error” for more information on framing errors.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

10.1.2.3

Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

RCIF interrupts are enabled by setting the following

bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the INT-

CON register

• GIE global interrupt enable bit of the INTCON

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

Note:

When the SPEN bit is set the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresponding TRIS bit and whether or not

the EUSART transmitter is enabled. The

PORT latch is disconnected from the

output driver so it is not possible to use the

TX/CK pin as a general purpose output.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 10.1.2.5

“Receive

Overrun

Error”

for

information on overrun errors.

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