PIC16F688-ISLASHML datasheet(61/204 Pages) MICROCHIP

61 / 204 page

DS41203E-page 59

PIC16F688

7.3.3

COMPARATOR INPUT SWITCH

The inverting input of the comparators may be switched

between two analog pins in the following modes:

• CM<2:0> = 001 (Comparator C1 only)

• CM<2:0> = 010 (Comparators C1 and C2)

In the above modes, both pins remain in analog mode

regardless of which pin is selected as the input. The CIS

bit of the CMCON0 register controls the comparator

input switch.

7.4

Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference specifications in Section 14.0

“Electrical Specifications” for more details.

7.5

Comparator Interrupt Operation

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an exclusive-

or gate (see Figure 7-2 and Figure 7-3). One latch is

updated with the comparator output level when the

CMCON0 register is read. This latch retains the value

until the next read of the CMCON0 register or the

occurrence of a Reset. The other latch of the mismatch

circuit is updated on every Q1 system clock. A

mismatch condition will occur when a comparator

output change is clocked through the second latch on

the Q1 clock cycle. The mismatch condition will persist,

holding the CxIF bit of the PIR1 register true, until either

the CMCON0 register is read or the comparator output

returns to the previous state.

Software will need to maintain information about the

status of the comparator output to determine the actual

change that has occurred.

The CxIF bit of the PIR1 register is the comparator

interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since it is also possible to write a ‘1’ to

this register, a simulated interrupt may be initiated.

The CxIE bit of the PIE1 register and the PEIE and GIE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interrupt is not enabled, although the CxIF bit of the

PIR1 register will still be set if an interrupt condition

occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of CMCON0. This will end the

mismatch condition. See Figures 7-6 and 7-7

Clear the CxIF interrupt flag.

A persistent mismatch condition will preclude clearing

the CxIF interrupt flag. Reading CMCON0 will end the

mismatch condition and allow the CxIF bit to be

cleared.

Note:

A write operation to the CMCON0 register

will also clear the mismatch condition

because

all

writes

include

read

operation at the beginning of the write

cycle.

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