PIC16F688-ISLASHML datasheet(94/204 Pages) MICROCHIP

94 / 204 page

PIC16F688

DS41203E-page 92

10.2

Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block

output (INTOSC). However, the INTOSC frequency

may drift as VDD or temperature changes, and this

directly affects the asynchronous baud rate. Two

methods may be used to adjust the baud rate clock, but

both require a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 3.5

“Internal Clock Modes” for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 10.3.1 “Auto-

Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

R-1

R/W-0

CSRC

TX9

TXEN(1)

SYNC

SENDB

BRGH

TRMT

TX9D

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

Master mode (clock generated internally from BRG)

Slave mode (clock from external source)

bit 6

TX9: 9-bit Transmit Enable bit

Selects 9-bit transmission

Selects 8-bit transmission

bit 5

TXEN: Transmit Enable bit(1)

= Transmit enabled

= Transmit disabled

bit 4

SYNC: EUSART Mode Select bit

= Synchronous mode

= Asynchronous mode

bit 3

SENDB: Send Break Character bit

Asynchronous mode:

= Send Sync Break on next transmission (cleared by hardware upon completion)

= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

= High speed

= Low speed

Synchronous mode:

Unused in this mode

bit 1

TRMT: Transmit Shift Register Status bit

= TSR empty

= TSR full

bit 0

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note

SREN/CREN overrides TXEN in Sync mode.

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