PIC16F688-ISLASHML datasheet(102/204 Pages) MICROCHIP

102 / 204 page

PIC16F688

DS41203E-page 100

10.3.2

AUTO-BAUD OVERFLOW

During the course of automatic baud detection, the

ABDOVF bit of the BAUDCTL register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPBRGH:SPBRG register

pair. After the ABDOVF has been set, the counter con-

tinues to count until the fifth rising edge is detected on

the RX pin. Upon detecting the fifth RX edge, the hard-

ware will set the RCIF interrupt flag and clear the

ABDEN bit of the BAUDCTL register. The RCIF flag

can be subsequently cleared by reading the RCREG.

The ABDOVF flag can be cleared by software directly.

To terminate the auto-baud process before the RCIF

flag is set, clear the ABDEN bit then clear the ABDOVF

bit. The ABDOVF bit will remain set if the ABDEN bit is

not cleared first.

10.3.3

AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCTL register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a wake-

up event independent of the CPU mode. A wake-up

event consists of a high-to-low transition on the RX/DT

line. (This coincides with the start of a Sync Break or a

wake-up signal character for the LIN protocol.)

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 10-7), and asynchronously if

the device is in Sleep mode (Figure 10-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

10.3.3.1

Special Considerations

Break Character

To avoid character errors or character fragments

during a wake-up event, the wake-up character must

be all zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS mode). The Sync Break (or

wake-up signal) character must be of sufficient length,

and be followed by a sufficient interval, to allow enough

time for the selected oscillator to start and provide

proper initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL.

FIGURE 10-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit set by user

Auto Cleared

Cleared due to User Read of RCREG

Note 1:

The EUSART remains in Idle while the WUE bit is set.

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