PIC18F23K20 datasheet(52/456 Pages) MICROCHIP

52 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 52

 2010 Microchip Technology Inc.

RCON: RESET CONTROL REGISTER

R/W-0

R/W-1

U-0

R/W-1

R-1

R/W-0

IPEN

SBOREN(1)

—RI

POR(2)

BOR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

IPEN: Interrupt Priority Enable bit

= Enable priority levels on interrupts

= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6

SBOREN: BOR Software Enable bit(1)

If BOREN<1:0> = 01:

= BOR is enabled

= BOR is disabled

If BOREN<1:0> = 00, 10 or 11:

Bit is disabled and read as ‘0’.

bit 5

Unimplemented: Read as ‘0’

bit 4

RI: RESET Instruction Flag bit

= The RESET instruction was not executed (set by firmware or Power-on Reset)

= The RESET instruction was executed causing a device Reset (must be set in firmware after a

code-executed Reset occurs)

bit 3

TO: Watchdog Time-out Flag bit

= Set by power-up, CLRWDT instruction or SLEEP instruction

= A WDT time-out occurred

bit 2

PD: Power-down Detection Flag bit

= Set by power-up or by the CLRWDT instruction

= Set by execution of the SLEEP instruction

bit 1

POR: Power-on Reset Status bit(2)

= No Power-on Reset occurred

= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit(3)

= A Brown-out Reset has not occurred (set by firmware only)

= A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)

Note 1:

When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’.

The actual Reset value of POR is determined by the type of device Reset. See the notes following this

See Table 4-3.

Note 1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set

to ‘1’ by firmware immediately after POR).

2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent

Power-on Resets may be detected.

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