PIC18F23K20 datasheet(48/456 Pages) MICROCHIP

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PIC18F2XK20/4XK20

DS41303G-page 48

 2010 Microchip Technology Inc.

3.4.3

RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator

block from the HFINTOSC multiplexer output. This

mode allows for controllable power conservation during

Idle periods.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then set

the SCS1 bit and execute SLEEP. It is recommended

that SCS0 also be cleared, although its value is

ignored, to maintain software compatibility with future

devices. The HFINTOSC multiplexer may be used to

select a higher clock frequency by modifying the IRCF

bits before executing the SLEEP instruction. When the

clock source is switched to the HFINTOSC multiplexer,

the primary oscillator is shut down and the OSTS bit is

cleared.

If the IRCF bits are set to any non-zero value, or the

INTSRC bit is set, the HFINTOSC output is enabled.

The IOFS bit becomes set, after the HFINTOSC output

becomes

stable,

after

interval

TIOBST

(parameter 39, Table 26-10). Clocks to the peripherals

continue while the HFINTOSC source stabilizes. If the

IRCF bits were previously at a non-zero value, or

INTSRC was set before the SLEEP instruction was exe-

cuted and the HFINTOSC source was already stable,

the IOFS bit will remain set. If the IRCF bits and

INTSRC are all clear, the HFINTOSC output will not be

enabled, the IOFS bit will remain clear and there will be

no indication of the current clock source.

When a wake event occurs, the peripherals continue to

be clocked from the HFINTOSC multiplexer output.

After a delay of TCSD following the wake event, the

CPU begins executing code being clocked by the

HFINTOSC multiplexer. The IDLEN and SCS bits are

not affected by the wake-up. The LFINTOSC source

will continue to run if either the WDT or the Fail-Safe

Clock Monitor is enabled.

3.5

Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is

triggered by any one of the following:

• an interrupt

•a Reset

• a watchdog time-out

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes (see Section 3.2 “Run Modes”, Section 3.3

“Sleep Mode” and Section 3.4 “Idle Modes”).

3.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode or the Sleep mode to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The PEIE bIt must also

be set If the desired interrupt enable bit is in a PIE reg-

ister. The exit sequence is initiated when the corre-

sponding interrupt flag bit is set.

The instruction immediately following the SLEEP

instruction is executed on all exits by interrupt from Idle

or Sleep modes. Code execution then branches to the

interrupt vector if the GIE/GIEH bit of the INTCON reg-

ister is set, otherwise code execution continues without

branching (see Section 9.0 “Interrupts”).

A fixed delay of interval TCSD following the wake event

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

3.5.2

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed

mode

(see

Section 3.2

“Run

Modes” and Section 3.3 “Sleep Mode”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 23.2 “Watchdog

Timer (WDT)”).

The WDT timer and postscaler are cleared by any one

of the following:

• executing a SLEEP instruction

• executing a CLRWDT instruction

• the loss of the currently selected clock source

when the Fail-Safe Clock Monitor is enabled

• modifying the IRCF bits in the OSCCON register

when the internal oscillator block is the device

clock source

3.5.3

EXIT BY RESET

Exiting Sleep and Idle modes by Reset causes code

execution to restart at address 0. See Section 4.0

“Reset” for more details.

The exit delay time from Reset to the start of code

execution depends on both the clock sources before

and after the wake-up and the type of oscillator. Exit

delays are summarized in Table 3-3.

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