PIC18F23K20 datasheet(43/456 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41303G-page 43

PIC18F2XK20/4XK20

3.0

POWER-MANAGED MODES

PIC18F2XK20/4XK20 devices offer a total of seven

operating modes for more efficient power manage-

ment. These modes provide a variety of options for

selective power conservation in applications where

resources may be limited (i.e., battery-powered

devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device

are clocked and sometimes, what speed. The Run and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

block); the Sleep mode does not use a clock source.

The power-managed modes include several power-

saving features offered on previous PIC® microcontroller

devices. One is the clock switching feature which allows

the controller to use the Timer1 oscillator in place of the

primary oscillator. Also included is the Sleep mode,

offered by all PIC® microcontroller devices, where all

device clocks are stopped.

3.1

Selecting Power-Managed Modes

Selecting

power-managed

mode

requires

two

decisions:

• Whether or not the CPU is to be clocked

• The selection of a clock source

The IDLEN bit of the OSCCON register controls CPU

clocking, while the SCS<1:0> bits of the OSCCON

bit settings, clock sources and affected modules are

summarized in Table 3-1.

3.1.1

CLOCK SOURCES

The SCS<1:0> bits allow the selection of one of three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the FOSC<3:0>

Configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block

3.1.2

ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins

the

OSCCON

The

SCS<1:0> bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit of the OSCCON register.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator select

bits, or changing the IDLEN bit, prior to issuing a SLEEP

instruction. If the IDLEN bit is already configured

correctly, it may only be necessary to perform a SLEEP

instruction to switch to the desired mode.

TABLE 3-1:

POWER-MANAGED MODES

Mode

OSCCON Bits

Module Clocking

Available Clock and Oscillator Source

IDLEN(1)

SCS<1:0>

CPU

Peripherals

Sleep

N/A

Off

None – All clocks are disabled

PRI_RUN

N/A

Clocked

Primary – LP, XT, HS, HSPLL, RC, EC and

Internal Oscillator Block(2).

This is the normal full power execution mode.

SEC_RUN

N/A

Clocked

Secondary – Timer1 Oscillator

RC_RUN

N/A

Clocked

Internal Oscillator Block(2)

PRI_IDLE

100

Off

Clocked

Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE

101

Off

Clocked

Secondary – Timer1 Oscillator

RC_IDLE

11x

Off

Clocked

Internal Oscillator Block(2)

Note 1:

IDLEN reflects its value when the SLEEP instruction is executed.

Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.

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