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SC68C652B датащи(PDF) 14 Page - NXP Semiconductors

номер детали SC68C652B
подробное описание детали  5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface
PDF  43 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC68C652B датащи(HTML) 14 Page - NXP Semiconductors

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SC68C652B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 2 November 2009
14 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
MCR[0] DTR, MCR[3] (OP2) and MCR[2] (OP1). Loopback test data is entered into the
transmit holding register via the user data bus interface, D0 to D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loopback connection. The receive UART converts the serial data back into parallel data
that is then made available at the user data interface D0 to D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free operation
of the UART transmit/receive circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
Fig 4.
Internal loopback mode diagram
CTSA, CTSB
TRANSMIT
FIFO
REGISTERS
TXA, TXB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
RXA, RXB
SC68C652B
TRANSMIT
SHIFT
REGISTER
XTAL2
XTAL1
002aab326
FLOW
CONTROL
LOGIC
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
RTSA, RTSB
DSRA, DSRB
DTRA, DTRB
RIA, RIB
(OP1A, OP1B)
CDA, CDB
(OP2A, OP2B)
IR
ENCODER
IR
DECODER
D0 to D7
R/W
RESET
A0 to A3
CS
IRQ
TXRDYA, TXRDYB
RXRDYA, RXRDYB



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