SC68C652B datasheet(8/43 Pages) NXP

8 / 43 page

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

8 of 43

NXP Semiconductors

SC68C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Functional description

The SC68C652B UART is pin-compatible with the SC68C2550B UART. It provides more

enhanced features. All additional features are provided through a special enhanced

feature register.

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the SC68C652B

UART can be read at any time during functional operation by the processor.

The SC68C652B can be placed in an alternate mode (FIFO mode) relieving the processor

of excessive software overhead by buffering received/transmitted characters. Both the

receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of

error status per byte for the receiver FIFO) and have selectable or programmable trigger

levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.

The SC68C652B has selectable hardware ﬂow control and software ﬂow control.

Hardware ﬂow control signiﬁcantly reduces software overhead and increases system

efﬁciency by automatically controlling serial data ﬂow using the RTSn output and CTSn

input signals. Software ﬂow control automatically controls data ﬂow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216

− 1).

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC68C652B package, and an external serial device. A

logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to conﬁgure, send

data, and/or receive data via UART channels A and B. Individual channel select functions

are shown in Table 3.

Table 3.

Channel selection using CS pin

UART channel

none

channel A

channel B

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