SC68C652B datasheet(9/43 Pages) NXP

9 / 43 page

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

9 of 43

NXP Semiconductors

SC68C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.2 Internal registers

The SC68C652B provides two sets of internal registers (A and B) consisting of

17 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a

user accessible scratchpad register (SPR), along with advanced feature registers EFR

and Xon1, Xon2, Xoff1 and Xoff2.

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

[3]

Enhanced Feature Register, Xon1, Xon2, and Xoff1, Xoff2 are accessible only when the LCR is set to ‘BFh’.

6.3 FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). With SC68C2550B devices, the user can set the receive trigger level, but

not the transmit trigger level. The SC68C652B provides independent trigger levels for both

receiver and transmitter. To remain compatible with SC68C2550B, the transmit interrupt

trigger level is set to 16 following a reset. It should be noted that the user can set the

transmit trigger levels by writing to the FCR register, but activation will not take place until

EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure

data is delivered to the external CPU. An interrupt is generated whenever the Receive

Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has not been reached.

Table 4.

Internal registers decoding

Read mode

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)[2]

LSB of Divisor Latch

MSB of Divisor Latch

Enhanced register set (EFR, Xon1, Xon2, Xoff1, Xoff2)[3]

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

SC68C652B датащи(PDF) 9 Page - NXP Semiconductors

SC68C652B датащи(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

датащи скачать

ссылки URL