PCF85133USLASH2DASLASH1 datasheet(12/41 Pages) NXP

12 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

12 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF85133 are timed by a frequency fclk

which either is derived from the built-in oscillator frequency fosc:

(4)

or equals an external clock frequency fclk(ext):

(5)

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output

from pin CLK provides the clock signal for cascaded PCF85133s in the system. After

power-up, pin SDA must be HIGH to guarantee that the clock starts.

7.5.2 External clock

Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the

external clock input.

A clock signal must always be supplied to the device; removing the clock may freeze the

LCD in a DC state.

7.6 Timing

The clock frequency fclk determines the LCD frame frequency ffr and is calculated as

follows:

(6)

The internal clock frequency fclk can be selected using pin FF. As a result 2 frame

frequencies are available: 82 Hz or 110 Hz (typical), see Table 6.

The timing of the PCF85133 organizes the internal data ﬂow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between all the PCF85133s in the system.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display register, the

LCD segment outputs and one column of the display RAM.

clk

osc

----------

clk

clk ext

()

Table 6.

LCD frame frequencies

Pin FF tied to

Typical clock frequency (Hz)

LCD frame frequency (Hz)

VDD

1970

VSS

2640

110

clk

---------

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